There has been significant research on various implementations of pad drivers for computer data communication and modern portable peripherals. The Universal Serial Bus (USB) standard is one of these common modern standards that result in tough specifications for pad drivers. Pad drivers ideally have a limited range of rise and fall times over a broad range of capacitive loads, process corners, supply voltages and temperature variations.
There are several known implementations of pad drivers. One known form of a current controlled pad driver is presented, in FIG. 1. In the pad driver of FIG. 1, the charging and discharging of the output is done through a current source. One drawback of this architecture is that the charging and discharging rates (slope=I/CL) are a function of the load capacitance, and thus, rise and fall times are load dependent.
Another known implementation is illustrated in FIG. 2. The pad driver of FIG. 2 has a negative feedback to control the charging and discharging rates. In the pad driver of FIG. 2, the output is compared with a reference signal by a high-speed rail-to-rail common mode amplifier. However, one drawback of this architecture is the need for a high-speed operational amplifier, which introduces unnecessary complexities to modern high-speed communication applications.
Yet another known pad driver circuit is shown in FIG. 3. In the pad driver of FIG. 3, current sources I1 and I2 are used to charge and discharge capacitors C1 and C2, respectively. This in turn charges and discharges points V1 and V2, respectively, at a constant charging and discharging rate (I1/C1=I2/C2). The source followers MN1 and MP2 buffer the constant-rate charging and discharging of nodes V1 and V2, respectively, to the output load capacitance CLOAD, thus, sustaining equal charging and discharging rates independent of the load value CLOAD. A potential problem with the configuration of FIG. 3 is that, during the charging phase, node V1 reaches VDD, but the output voltage will remain at VDD−VTN such that MN1 is just on (wherein VTN is the threshold voltage of the NMOS driver MN1).
In addition, during discharging, node V2 drops to zero, but the output voltage will drop to VTP such that MP2 is just on, (wherein VTP is the threshold voltage of the PMOS driver MP2). In order to address these problems, the pad driver circuit of FIG. 3 uses two amplifiers. Amplifier A1 turns on the switch MP1 during charging when the voltage at node V1 approaches VDD. In this case, the capacitive load charges through the on-resistance of MP1 to VDD. Amplifier A2 is used to turn on the switch MN2 during discharging when the voltage at node V2 approaches zero. In this case, the capacitive load discharges through the on-resistance of MN2 to zero. However, this adds to the complexity of the circuit design because of the two high-speed amplifiers A1 and A2. Another drawback of this architecture arises during the charging and discharging phases when the output voltage approaches VDD−VTN and VTP, respectively. Under these conditions, the charging and discharging process becomes dependent on the load capacitance and the on-resistance of switches MP1 and MN2, respectively.
Therefore, a need exists for improved pad drivers.